TNKernel port for the TI MSP430x CPU
1. Hardware specifics
The MSP430x CPU family has a 16-bit data bus, and TNKernel port for MSP430x uses 16 levels of priority.
Priorities 0 (highest) and 15 (lowest) are reserved by the system for the internal usage. The user may create a tasks with priorities 1…14.
TNKernel port for MXP430x does not supports nested interrupts.
2. Context switching
With the MXP430x core, TNKernel uses a software interrupt source with the minimal priority (for MSP430F6638 CPU - I/O Port P4 and bit P4.7 interrupt) to request the context switch.
This approach makes the system context switch unified for the both interrupts context switch and tasks (non-interrupt) context switch and accelerates the registers save/restore procedure for non-interrupt context switch.
At the system start (function tn_start_exe()), the context switch procedure is called directly to keep a correct sequence of the registers restoring.
TNKernel port for MXP430x core comes with base example. The example demonstrates the base OS functionality (tasks, UART, etc).
The RTOS was tested with MSP430F6638 CPU. For the system tick interrupt (with the period 2 ms) the Timer1_A0 was used, CPU clock = 20MHz.
For the example, UART uses interrupts to processing TX queue and to put a received data into the RX queue.
This is TNKernel v.2.6 source code for TI MSP430x CPU.
The file also contains an example for MSP430F6638 CPU MCU and the project for the IAR MSP430 v.5.xx compiler