Description

1. Hardware-specific information

   With a Cortex-M3 core, TNKernel uses SysTick timer as system timer source.
   TNKernel operates in a privileged mode and uses separate PSP (Process Stack Pointer)  for each task.

2. Nested interrupts

    A Cortex-M3 Nested Vectored Interrupt Controller (NVIC) is a part of the CPU and performs nested interrupt processing with two most important features:

• at the interrupt entry, the CPU automatically saves processor state (registers PC, xPSR, r0-r3, r12, LR), which is pushed on to the stack.
  
  
• the processor doesn't automatically disabled interrupts, when it takes an exception (interrupt). It means that RTOS must support nested interrupts.
  

   A TNKernel for Cortex-M3 completely supports nested interrupts. To recognize a nested interrupt condition, a two macros are used:



   A function tn_inside_int() uses Cortex-M3 NVIC status register VECTACTIVE flag:

3. Context switching with Cortex-M3

   With Cortex-M3 core, TNKernel uses unified approach to request context switch - an invoking SVPend exception (interrupt).
  A SVPend exception priority is minimal (0xFF) and SVPend will be processed last in the nested interrupts chain.

   Inside an interrupt processing or inside TNKernel semaphores, queues and other similar operations, when a context switch is required under certain conditions, the system calls SVPend.

   An each interrupt handler function calls a tn_int_exit() function as the last operation. A  tn_int_exit()function is a just PendSV exception request:

   Inside the SVPend interrupt handler, the system checks a context switching conditions and performs the operation, if it is necessarily.

   A context switch routine is similar to the Example 5-5 (Implement a simple context switcher) of the Cortex™-M3 Technical Reference Manual (ARM DDI 0337E document).
   The full register set is saved only at the context switch (at the interrupt entry, the CPU automatically saves some registers -see above).

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